1. Field of the Invention
This invention relates to a capacitor structure in a semiconductor memory cell using a ferroelectric thin film and a method for fabricating it, and more specifically, to a capacitor structure in a semiconductor memory cell in form of a nonvolatile memory cell (called FERAM) or DRAM using a ferroelectric thin film and a method for fabricating it.
2. Description of the Related Art
Laborious researches for applications of nonvolatile memory using ferroelectric thin films have been progressed recently along with developments in film making technologies. Nonvolatile memory utilizes quick inversion of polarization and residual polarization of a ferroelectric thin film, and permits high-speed rewriting. Nonvolatile memory devices using ferroelectric films under current researches can be classified into a group relying on detection of changes in amount of electric charge accumulated in a ferroelectric capacitor and another group relying on detection of changes in resistance of a semiconductor caused by spontaneous polarization of a ferroelectric material. The invention relates to a semiconductor memory cell belonging to the former group.
Nonvolatile memory cells configured to detect changes in accumulated electric charge in a ferroelectric capacitor basically comprises a ferroelectric capacitor and a selection transistor. The ferroelectric capacitor is made of a lower electrode, upper electrode, and a ferroelectric thin film between the electrodes. Writing and reading data with a nonvolatile memory cell of this type relies on a P-E hysteresis loop of the ferroelectric material as shown in FIG. 1. When an external electric field is applied to and then removed from the ferroelectric thin film, the ferroelectric thin film exhibits spontaneous polarization. The residual polarization of the ferroelectric thin film becomes +P.sub.r when a plus external field is applied, and becomes -P.sub.r when a minus external field is applied. The state where the residual polarization is +P.sub.r (see D in FIG. 1) is determined as "0", and the state where the residual polarization is -P.sub.r (see A in FIG. 1) is determined as "1".
For discriminating whether the state is "1" or "0", a plus external field, for example, is applied to the ferroelectric thin film. As a result, polarization of the ferroelectric thin film is changed to the state "C" in FIG. 1. Then, if data is "0", polarization of the ferroelectric thin film changes from "D" to "C". If data is "1", polarization of the ferroelectric thin film changes from "A" through "B" to "C". When data is "0", polarization of the ferroelectric thin film is not inverted. When data is "1", inversion of polarization occurs in the ferroelectric thin film. As a result, a difference is produced in amount of moving charge in response to a difference in accumulated electric charge (state of polarization) in the ferroelectric capacitor. By turning on the selection transistor of a selected memory cell, the accumulated electric charge is detected as a bit line potential. When the external electric field is changed to 0 after data is read out, the state of polarization of the ferroelectric thin film becomes "D" in FIG. 1 whichever of "0" and "1" is the data. Therefore, when the data is "1", a minus external electric field is applied to change the state from "D" through "E" to "A" permitting data "1" to be written.
In order to realize higher integration of nonvolatile semiconductor memory, the area of the ferroelectric thin film must be increased. In DRAMs, a high dielectric thin film similar to the ferroelectric thin film currently used in nonvolatile semiconductor memory will be used when a high integration around 1 Gbits is desired, and there are various proposals for its capacitor structure. For example, a pedestal-type DRAM using SrTiO.sub.3 as a high dielectric thin film is known from the literature "A Gbit-scale DRAM stacked capacitor technology with ECR MOCVD SrTiO.sub.3 and RIE patterned RuO.sub.2 /TiN storage nodes", P-Y Lesaicherre, et al., IEDM 94-841, 34.1.1. In a DRAM cell disclosed by the literature, as schematically shown in a fragmentary cross-sectional view of FIG. 2, the lower electrode made of RuO.sub.2 has the form of a column patterned by RIE. By using the column-shaped lower electrode, the area of the high dielectric thin film covering the lower electrode can be increased.
In a DRAM using a high dielectric thin film, accumulated charge and applied voltage have a linear relationship. In contrast, in a semiconductor memory cell using a ferroelectric thin film, accumulated electric charge and applied voltage are non-linearly related as shown in FIG. 1, and the memory cell has a hysteresis characteristics. Additionally, the characteristic of the ferroelectric thin film is sensitive to the surface condition of the lower electrode. If the technique shown in the above-introduced literature is applied to a semiconductor memory cell using a ferroelectric thin film, that is, if the ferroelectric thin film is formed on the lower electrode in form of a column patterned by RIE, the characteristic of the ferroelectric thin film will be degraded because the surface of the lower electrode of this type is usually coarse due to damages and usually exhibits a bad surface morphology.